In the data processing environment, a large percentage of a central processor's time is spent in idle loops waiting for one or more I/O devices to complete an operation or for further input to the processor from an operator. In a system where AC power is being used to provide power to the central processor, the time spent in idle loops is not very critical. However, in an operating environment wherein power is being supplied to the central processor from a battery, time spent in idle loops by the central processor needlessly wastes battery power. Consequently, it would be desirable to prevent a central processor from performing idle loops while waiting for the completion of an operation by an I/O device or when waiting for further input to the processor from an operator. As small computers, especially those which are portable, become more prevalent, the need to conserve battery power becomes increasingly important.
Typically, a battery operated computer uses complementary metal-oxide-silicon (CMOS) circuits to reduce power consumption. However, in order to take full advantage of these CMOS circuits, the circuits must not be clocked when their usage is not required. As is well known, the characteristics of CMOS circuits provide very low standby power consumption when they are not being clocked. In order to fully realize this power saving advantage, application programs and the operating system software that are running on the data processing system must be able to stop the system clocks when the central processor is waiting for the completion of an I/O operation or for further operator input.
U.S. Pat. No. 3,941,989 discloses one method for reducing power consumption in calculators wherein lower duty cycle power and lower duty cycle clock pulses are supplied during the calculator display mode. While the calculator is in an execute mode, continuous power and a high rate clock are supplied. If an execute mode is not initiated within a selected time interval, the duty cycle of both the power and the clock are lowered even further than that provided during the display mode.
U.S. Pat. No. 4,435,761 disclose a data processing apparatus having both a data transmitting and receiving unit for transferring data, and a processing unit for processing the data. Means are provided for stopping the supply of a control clock signal while the transmission of data is in progress.
Another approach to conserving energy in data processing systems is shown in both U.S. Pat. Nos. 4,279,020 and 4,455,623. In the former, when the central processor completes operation, it provides an output signal to a power-down sub-circuit of a power supply which then removes power from the central processor. In this manner, power is not supplied to the processor when it is not operating. In the latter, the current consumption of a microprocessor is decreased by a switch which connects it to a power supply only when a control signal is received which indicates that the microprocessor is to execute a program. Specifically, an electronic switch is used to switch to a non-conductive state unless a control signal is received. For software programs which require a greater time for execution than the duration of the control signal, the microprocessor supplies a signal to the electronic switch thereby keeping it in the conductive state until the software program has been fully executed. A similar approach is shown in U.S. Pat. No. 4,203,153.
U.S. Pat. No. 4,409,665 discloses the conservation of power in a calculator having a memory utilizing CMOS circuits. Incorporation of two switched voltages and a single non-switched voltage enables power to be switched off to the calculator's logic, display interface and keystroke detect circuitry, while power is maintained to the memory. In other embodiments, multiple modes such as off mode, display only mode, process only mode, and a display and process mode are used to optimize power dissipation. The calculator powers up into the display mode until a keystroke is detected. At that time, power is supplied to the processor until completion of the processing. This power conservation is effected using a first power switching means connected to a first circuit group and to a power consumption controller, and a second power switching means connected to the power consumption controller and to a second circuit group.